Language:
English
繁體中文
Help
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
Evolving OpenMP for Evolving Archite...
~
Valero-Lara, Pedro.
Evolving OpenMP for Evolving Architectures = 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /
Record Type:
Language materials, printed : Monograph/item
Title/Author:
Evolving OpenMP for Evolving Architectures/ edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta.
Reminder of title:
14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /
other author:
de Supinski, Bronis R.
Description:
X, 253 p. 103 illus.online resource. :
Contained By:
Springer Nature eBook
Subject:
Microprocessors. -
Online resource:
https://doi.org/10.1007/978-3-319-98521-3
ISBN:
9783319985213
Evolving OpenMP for Evolving Architectures = 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /
Evolving OpenMP for Evolving Architectures
14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /[electronic resource] :edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta. - 1st ed. 2018. - X, 253 p. 103 illus.online resource. - Programming and Software Engineering ;11128. - Programming and Software Engineering ;8987.
Best Paper -- The Impact of Taskyield on the Design of Tasks Communicating through MPI -- Loops and OpenMP -- OpenMP Loop Scheduling Revisited: Making a Case for More Schedules -- A Proposal for Loop-Transformation Pragmas -- Extending OpenMP to Facilitate Loop Optimization -- OpenMP in Heterogeneous Systems -- Manage OpenMP GPU Data Environment under Unified Address Space -- OpenMP 4.5 Validation and Verification Suite for Device Offload -- Trade-o_ of offloading to FPGA in OpenMP Task-based programming -- OpenMP Improvements and Innovations -- Compiler Optimizations For OpenMP -- Supporting Function Variants in OpenMP -- Towards an OpenMP Specification for Critical Real-time Systems -- OpenMP User Experiences: Applications and Tools -- Performance Tuning to Close Ninja Gap for Accelerator Physics Emulation System (APES) on Intel Xeon Phi Processors -- Visualization of OpenMP Task Dependencies using Intel Advisor Flow Graph Analyzer -- A Semantics-Driven Approach to Improving DataRaceBench's OpenMP Standard Coverage -- Tasking Evaluations -- On the Impact of OpenMP Task Granularity -- Mapping OpenMP to a Distributed Tasking Runtime -- Assessing Task-to-Data Affinity in the LLVM OpenMP Runtime.
This book constitutes the proceedings of the 14th International Workshop on Open MP, IWOMP 2018, held in Barcelona, Spain, in September 2018. The 16 full papers presented in this volume were carefully reviewed and selected for inclusion in this book. The papers are organized in topical sections named: best paper; loops and OpenMP; OpenMP in heterogeneous systems; OpenMP improvements and innovations; OpenMP user experiences: applications and tools; and tasking evaluations.
ISBN: 9783319985213
Standard No.: 10.1007/978-3-319-98521-3doiSubjects--Topical Terms:
632481
Microprocessors.
LC Class. No.: TK7895.M5
Dewey Class. No.: 004.1
Evolving OpenMP for Evolving Architectures = 14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /
LDR
:03233nam a22004095i 4500
001
987892
003
DE-He213
005
20200706133740.0
007
cr nn 008mamaa
008
201225s2018 gw | s |||| 0|eng d
020
$a
9783319985213
$9
978-3-319-98521-3
024
7
$a
10.1007/978-3-319-98521-3
$2
doi
035
$a
978-3-319-98521-3
050
4
$a
TK7895.M5
072
7
$a
UYF
$2
bicssc
072
7
$a
COM011000
$2
bisacsh
072
7
$a
UYF
$2
thema
082
0 4
$a
004.1
$2
23
245
1 0
$a
Evolving OpenMP for Evolving Architectures
$h
[electronic resource] :
$b
14th International Workshop on OpenMP, IWOMP 2018, Barcelona, Spain, September 26–28, 2018, Proceedings /
$c
edited by Bronis R. de Supinski, Pedro Valero-Lara, Xavier Martorell, Sergi Mateo Bellido, Jesus Labarta.
250
$a
1st ed. 2018.
264
1
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2018.
300
$a
X, 253 p. 103 illus.
$b
online resource.
336
$a
text
$b
txt
$2
rdacontent
337
$a
computer
$b
c
$2
rdamedia
338
$a
online resource
$b
cr
$2
rdacarrier
347
$a
text file
$b
PDF
$2
rda
490
1
$a
Programming and Software Engineering ;
$v
11128
505
0
$a
Best Paper -- The Impact of Taskyield on the Design of Tasks Communicating through MPI -- Loops and OpenMP -- OpenMP Loop Scheduling Revisited: Making a Case for More Schedules -- A Proposal for Loop-Transformation Pragmas -- Extending OpenMP to Facilitate Loop Optimization -- OpenMP in Heterogeneous Systems -- Manage OpenMP GPU Data Environment under Unified Address Space -- OpenMP 4.5 Validation and Verification Suite for Device Offload -- Trade-o_ of offloading to FPGA in OpenMP Task-based programming -- OpenMP Improvements and Innovations -- Compiler Optimizations For OpenMP -- Supporting Function Variants in OpenMP -- Towards an OpenMP Specification for Critical Real-time Systems -- OpenMP User Experiences: Applications and Tools -- Performance Tuning to Close Ninja Gap for Accelerator Physics Emulation System (APES) on Intel Xeon Phi Processors -- Visualization of OpenMP Task Dependencies using Intel Advisor Flow Graph Analyzer -- A Semantics-Driven Approach to Improving DataRaceBench's OpenMP Standard Coverage -- Tasking Evaluations -- On the Impact of OpenMP Task Granularity -- Mapping OpenMP to a Distributed Tasking Runtime -- Assessing Task-to-Data Affinity in the LLVM OpenMP Runtime.
520
$a
This book constitutes the proceedings of the 14th International Workshop on Open MP, IWOMP 2018, held in Barcelona, Spain, in September 2018. The 16 full papers presented in this volume were carefully reviewed and selected for inclusion in this book. The papers are organized in topical sections named: best paper; loops and OpenMP; OpenMP in heterogeneous systems; OpenMP improvements and innovations; OpenMP user experiences: applications and tools; and tasking evaluations.
650
0
$a
Microprocessors.
$3
632481
650
0
$a
Software engineering.
$3
562952
650
0
$a
Logic design.
$3
561473
650
0
$a
Computers.
$3
565115
650
1 4
$a
Processor Architectures.
$3
669787
650
2 4
$a
Software Engineering/Programming and Operating Systems.
$3
669780
650
2 4
$a
Logic Design.
$3
670915
650
2 4
$a
Models and Principles.
$3
669634
700
1
$a
de Supinski, Bronis R.
$4
edt
$4
http://id.loc.gov/vocabulary/relators/edt
$3
1113510
700
1
$a
Valero-Lara, Pedro.
$e
editor.
$1
https://orcid.org/0000-0002-1479-4310
$4
edt
$4
http://id.loc.gov/vocabulary/relators/edt
$3
1280267
700
1
$a
Martorell, Xavier.
$e
editor.
$4
edt
$4
http://id.loc.gov/vocabulary/relators/edt
$3
1280268
700
1
$a
Mateo Bellido, Sergi.
$e
editor.
$4
edt
$4
http://id.loc.gov/vocabulary/relators/edt
$3
1280269
700
1
$a
Labarta, Jesus.
$4
edt
$4
http://id.loc.gov/vocabulary/relators/edt
$3
678723
710
2
$a
SpringerLink (Online service)
$3
593884
773
0
$t
Springer Nature eBook
776
0 8
$i
Printed edition:
$z
9783319985206
776
0 8
$i
Printed edition:
$z
9783319985220
830
0
$a
Programming and Software Engineering ;
$v
8987
$3
1253476
856
4 0
$u
https://doi.org/10.1007/978-3-319-98521-3
912
$a
ZDB-2-SCS
912
$a
ZDB-2-SXCS
912
$a
ZDB-2-LNC
950
$a
Computer Science (SpringerNature-11645)
950
$a
Computer Science (R0) (SpringerNature-43710)
based on 0 review(s)
Multimedia
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login