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Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Thread and Data Mapping for Multicore Systems/ by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux.
其他題名:	Improving Communication and Memory Accesses /
作者:	H. M. Cruz, Eduardo.
其他作者:	Diener, Matthias.
面頁冊數:	IX, 54 p. 34 illus.online resource. :
Contained By:	Springer Nature eBook
標題:	Computer hardware. -
電子資源:	https://doi.org/10.1007/978-3-319-91074-1
ISBN:	9783319910741

Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /
H. M. Cruz, Eduardo.

Thread and Data Mapping for Multicore SystemsImproving Communication and Memory Accesses /[electronic resource] :by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux. - 1st ed. 2018. - IX, 54 p. 34 illus.online resource. - SpringerBriefs in Computer Science,2191-5768. - SpringerBriefs in Computer Science,.

preface -- chapter 1: introduction -- chapter 2: Sharing-aware mapping and parallel architectures -- chapter 3: Sharing-aware mapping and parallel applications -- chapter 4: Sharing-Aware mapping methods -- chapter 5: Improving performance with Sharing-Aware mapping -- chapter 6: conclusion and research prospects -- index.

This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

ISBN: 9783319910741

Standard No.: 10.1007/978-3-319-91074-1doiSubjects--Topical Terms:

1069242
Computer hardware.

LC Class. No.: QA75.5-76.95

Dewey Class. No.: 004

Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /
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