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Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Thread and Data Mapping for Multicore Systems/ by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux.
Reminder of title:	Improving Communication and Memory Accesses /
Author:	H. M. Cruz, Eduardo.
other author:	Diener, Matthias.
Description:	IX, 54 p. 34 illus.online resource. :
Contained By:	Springer Nature eBook
Subject:	Computer hardware. -
Online resource:	https://doi.org/10.1007/978-3-319-91074-1
ISBN:	9783319910741

Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /
H. M. Cruz, Eduardo.

Thread and Data Mapping for Multicore SystemsImproving Communication and Memory Accesses /[electronic resource] :by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux. - 1st ed. 2018. - IX, 54 p. 34 illus.online resource. - SpringerBriefs in Computer Science,2191-5768. - SpringerBriefs in Computer Science,.

preface -- chapter 1: introduction -- chapter 2: Sharing-aware mapping and parallel architectures -- chapter 3: Sharing-aware mapping and parallel applications -- chapter 4: Sharing-Aware mapping methods -- chapter 5: Improving performance with Sharing-Aware mapping -- chapter 6: conclusion and research prospects -- index.

This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

ISBN: 9783319910741

Standard No.: 10.1007/978-3-319-91074-1doiSubjects--Topical Terms:

1069242
Computer hardware.

LC Class. No.: QA75.5-76.95

Dewey Class. No.: 004

Thread and Data Mapping for Multicore Systems = Improving Communication and Memory Accesses /
LDR:02341nam a22004095i 4500 001 990503
003 DE-He213
005 20200703160835.0
007 cr nn 008mamaa
008 201225s2018 gw | s |||| 0|eng d
020 $a 9783319910741 $9 978-3-319-91074-1
024 7 $a 10.1007/978-3-319-91074-1 $2 doi
035 $a 978-3-319-91074-1
050 4 $a QA75.5-76.95
050 4 $a TK7885-7895
072 7 $a UK $2 bicssc
072 7 $a COM067000 $2 bisacsh
072 7 $a UK $2 thema
082 0 4 $a 004 $2 23
100 1 $a H. M. Cruz, Eduardo. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1282201
245 1 0 $a Thread and Data Mapping for Multicore Systems $h [electronic resource] : $b Improving Communication and Memory Accesses / $c by Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux.
250 $a 1st ed. 2018.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2018.
300 $a IX, 54 p. 34 illus. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a SpringerBriefs in Computer Science, $x 2191-5768
505 0 $a preface -- chapter 1: introduction -- chapter 2: Sharing-aware mapping and parallel architectures -- chapter 3: Sharing-aware mapping and parallel applications -- chapter 4: Sharing-Aware mapping methods -- chapter 5: Improving performance with Sharing-Aware mapping -- chapter 6: conclusion and research prospects -- index.
520 $a This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.
650 0 $a Computer hardware. $3 1069242
650 0 $a Software engineering. $3 562952
650 1 4 $a Computer Hardware. $3 669779
650 2 4 $a Software Engineering/Programming and Operating Systems. $3 669780
700 1 $a Diener, Matthias. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1207072
700 1 $a O. A. Navaux, Philippe. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1282202
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783319910734
776 0 8 $i Printed edition: $z 9783319910758
830 0 $a SpringerBriefs in Computer Science, $x 2191-5768 $3 1255334
856 4 0 $u https://doi.org/10.1007/978-3-319-91074-1
912 $a ZDB-2-SCS
912 $a ZDB-2-SXCS
950 $a Computer Science (SpringerNature-11645)
950 $a Computer Science (R0) (SpringerNature-43710)