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Design Techniques for Mash Continuou...
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Silva-Martinez, Jose.
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators/ by Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez.
作者:
Liu, Qiyuan.
其他作者:
Edward, Alexander.
面頁冊數:
XVI, 208 p. 184 illus., 71 illus. in color.online resource. :
Contained By:
Springer Nature eBook
標題:
Electronic circuits. -
電子資源:
https://doi.org/10.1007/978-3-319-77225-7
ISBN:
9783319772257
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
Liu, Qiyuan.
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
[electronic resource] /by Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez. - 1st ed. 2018. - XVI, 208 p. 184 illus., 71 illus. in color.online resource.
Introduction -- Analog-To-Digital and Digital-To-Analog Converters -- Delta-Sigma Modulators -- Design Considerations Of Mash CT-ΔΣM -- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS -- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS -- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer -- Conclusion.
This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT-ΔΣM), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.
ISBN: 9783319772257
Standard No.: 10.1007/978-3-319-77225-7doiSubjects--Topical Terms:
563332
Electronic circuits.
LC Class. No.: TK7888.4
Dewey Class. No.: 621.3815
Design Techniques for Mash Continuous-Time Delta-Sigma Modulators
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Introduction -- Analog-To-Digital and Digital-To-Analog Converters -- Delta-Sigma Modulators -- Design Considerations Of Mash CT-ΔΣM -- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS -- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS -- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer -- Conclusion.
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