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Low-Power Design and Power-Aware Verification

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Low-Power Design and Power-Aware Verification/ by Progyna Khondkar.
Author:	Khondkar, Progyna.
Description:	XV, 155 p. 19 illus., 12 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-3-319-66619-8
ISBN:	9783319666198

Low-Power Design and Power-Aware Verification
Khondkar, Progyna.

Low-Power Design and Power-Aware Verification[electronic resource] /by Progyna Khondkar. - 1st ed. 2018. - XV, 155 p. 19 illus., 12 illus. in color.online resource.

1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .

Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .

ISBN: 9783319666198

Standard No.: 10.1007/978-3-319-66619-8doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Low-Power Design and Power-Aware Verification
LDR:02929nam a22003975i 4500 001 996422
003 DE-He213
005 20200706013634.0
007 cr nn 008mamaa
008 201225s2018 gw | s |||| 0|eng d
020 $a 9783319666198 $9 978-3-319-66619-8
024 7 $a 10.1007/978-3-319-66619-8 $2 doi
035 $a 978-3-319-66619-8
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Khondkar, Progyna. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1287587
245 1 0 $a Low-Power Design and Power-Aware Verification $h [electronic resource] / $c by Progyna Khondkar.
250 $a 1st ed. 2018.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2018.
300 $a XV, 155 p. 19 illus., 12 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a 1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References. .
520 $a Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers. .
650 0 $a Electronic circuits. $3 563332
650 0 $a Software engineering. $3 562952
650 0 $a Microprocessors. $3 632481
650 0 $a Computer software—Reusability. $3 1254984
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Software Engineering. $3 669632
650 2 4 $a Processor Architectures. $3 669787
650 2 4 $a Performance and Reliability. $3 669802
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783319666181
776 0 8 $i Printed edition: $z 9783319666204
776 0 8 $i Printed edition: $z 9783319882864
856 4 0 $u https://doi.org/10.1007/978-3-319-66619-8
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)