國立虎尾科技大學 |

Logic Synthesis for Finite State Machines Based on Linear Chains of States = Foundations, Recent Developments and Challenges /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Logic Synthesis for Finite State Machines Based on Linear Chains of States/ by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski.
其他題名:	Foundations, Recent Developments and Challenges /
作者:	Barkalov, Alexander.
其他作者:	Titarenko, Larysa.
面頁冊數:	VIII, 225 p. 145 illus.online resource. :
Contained By:	Springer Nature eBook
標題:	Computational intelligence. -
電子資源:	https://doi.org/10.1007/978-3-319-59837-6
ISBN:	9783319598376

Logic Synthesis for Finite State Machines Based on Linear Chains of States = Foundations, Recent Developments and Challenges /
Barkalov, Alexander.

Logic Synthesis for Finite State Machines Based on Linear Chains of StatesFoundations, Recent Developments and Challenges /[electronic resource] :by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski. - 1st ed. 2018. - VIII, 225 p. 145 illus.online resource. - Studies in Systems, Decision and Control,1132198-4182 ;. - Studies in Systems, Decision and Control,27.

Introduction -- Finite state machines and ﬁeld-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units.

ISBN: 9783319598376

Standard No.: 10.1007/978-3-319-59837-6doiSubjects--Topical Terms:

568984
Computational intelligence.

LC Class. No.: Q342

Dewey Class. No.: 006.3

Logic Synthesis for Finite State Machines Based on Linear Chains of States = Foundations, Recent Developments and Challenges /
LDR:02813nam a22004095i 4500 001 999199
003 DE-He213
005 20200703055502.0
007 cr nn 008mamaa
008 201225s2018 gw | s |||| 0|eng d
020 $a 9783319598376 $9 978-3-319-59837-6
024 7 $a 10.1007/978-3-319-59837-6 $2 doi
035 $a 978-3-319-59837-6
050 4 $a Q342
072 7 $a UYQ $2 bicssc
072 7 $a TEC009000 $2 bisacsh
072 7 $a UYQ $2 thema
082 0 4 $a 006.3 $2 23
100 1 $a Barkalov, Alexander. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 681736
245 1 0 $a Logic Synthesis for Finite State Machines Based on Linear Chains of States $h [electronic resource] : $b Foundations, Recent Developments and Challenges / $c by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski.
250 $a 1st ed. 2018.
264 1 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2018.
300 $a VIII, 225 p. 145 illus. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a Studies in Systems, Decision and Control, $x 2198-4182 ; $v 113
505 0 $a Introduction -- Finite state machines and ﬁeld-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.
520 $a This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units.
650 0 $a Computational intelligence. $3 568984
650 0 $a Electronic circuits. $3 563332
650 1 4 $a Computational Intelligence. $3 768837
650 2 4 $a Circuits and Systems. $3 670901
700 1 $a Titarenko, Larysa. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 681737
700 1 $a Bieganowski, Jacek. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1290777
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9783319598369
776 0 8 $i Printed edition: $z 9783319598383
776 0 8 $i Printed edition: $z 9783319867144
830 0 $a Studies in Systems, Decision and Control, $x 2198-4182 ; $v 27 $3 1254124
856 4 0 $u https://doi.org/10.1007/978-3-319-59837-6
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)