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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip/ by Zheng Wang, Anupam Chattopadhyay.
作者:	Wang, Zheng.
其他作者:	Chattopadhyay, Anupam.
面頁冊數:	XX, 197 p. 104 illus., 72 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic circuits. -
電子資源:	https://doi.org/10.1007/978-981-10-1073-6
ISBN:	9789811010736

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Wang, Zheng.

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip[electronic resource] /by Zheng Wang, Anupam Chattopadhyay. - 1st ed. 2018. - XX, 197 p. 104 illus., 72 illus. in color.online resource. - Computer Architecture and Design Methodologies,2367-3478. - Computer Architecture and Design Methodologies,.

Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .

ISBN: 9789811010736

Standard No.: 10.1007/978-981-10-1073-6doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
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