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ASIC Design and Synthesis = RTL Design Using Verilog /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	ASIC Design and Synthesis / by Vaibbhav Taraate.
Reminder of title:	RTL Design Using Verilog /
Author:	Taraate, Vaibbhav.
Description:	XXI, 330 p. 311 illus., 184 illus. in color.online resource. :
Contained By:	Springer Nature eBook
Subject:	Electronic circuits. -
Online resource:	https://doi.org/10.1007/978-981-33-4642-0
ISBN:	9789813346420

ASIC Design and Synthesis = RTL Design Using Verilog /
Taraate, Vaibbhav.

ASIC Design and Synthesis RTL Design Using Verilog /[electronic resource] :by Vaibbhav Taraate. - 1st ed. 2021. - XXI, 330 p. 311 illus., 184 illus. in color.online resource.

Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

ISBN: 9789813346420

Standard No.: 10.1007/978-981-33-4642-0doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

ASIC Design and Synthesis = RTL Design Using Verilog /
LDR:02825nam a22003975i 4500 001 1051710
003 DE-He213
005 20210619142709.0
007 cr nn 008mamaa
008 220103s2021 si | s |||| 0|eng d
020 $a 9789813346420 $9 978-981-33-4642-0
024 7 $a 10.1007/978-981-33-4642-0 $2 doi
035 $a 978-981-33-4642-0
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Taraate, Vaibbhav. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1109142
245 1 0 $a ASIC Design and Synthesis $h [electronic resource] : $b RTL Design Using Verilog / $c by Vaibbhav Taraate.
250 $a 1st ed. 2021.
264 1 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2021.
300 $a XXI, 330 p. 311 illus., 184 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520 $a This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
650 0 $a Electronic circuits. $3 563332
650 0 $a Microprogramming . $3 1257366
650 0 $a Logic design. $3 561473
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Control Structures and Microprogramming. $3 669788
650 2 4 $a Logic Design. $3 670915
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9789813346413
776 0 8 $i Printed edition: $z 9789813346437
776 0 8 $i Printed edition: $z 9789813346444
856 4 0 $u https://doi.org/10.1007/978-981-33-4642-0
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)