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A Secure SoC Platform for Security Assessments in FPGAs.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	A Secure SoC Platform for Security Assessments in FPGAs./
Author:	Nicholas, Geraldine Shirley.
Description:	1 online resource (113 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 84-11, Section: B.
Contained By:	Dissertations Abstracts International84-11B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798379453572

A Secure SoC Platform for Security Assessments in FPGAs.
Nicholas, Geraldine Shirley.

A Secure SoC Platform for Security Assessments in FPGAs. - 1 online resource (113 pages)

Source: Dissertations Abstracts International, Volume: 84-11, Section: B.

Thesis (Ph.D.)--The University of North Carolina at Charlotte, 2023.

Includes bibliographical references

With the rapid increase in connected devices and SoC design architecture being used in diverse platforms, they become potential targets to gain unauthorized access for data and privacy invasion. Therefore, heterogeneous SoC architecture raises security concerns in addition to the benefits they offer with improved throughput. They are susceptible to side-channel attacks where secure information is extracted through communication channels. Crypto algorithms implemented for secure authentication tend to leak sensitive information jeopardizing system security. Memory corruption vulnerabilities, code injection, buffer overflow attacks and other software-based attacks through untrusted channels tend to control the flow of the application with malicious data. Though traditional defense mechanisms have been implemented they are all still vulnerable to side-channel attacks.Secure measures to protect the interfaces and data propagation through different channels are critical and building a resilient model consists of the on-chip security factors. In this work, a platform based SoC model is implemented to meet the security objectives using the RISC-V architecture in which an information flow tracking module tracks the flow of data for the system's integrity along with crypto engines and a secure boot mechanism for secure device authentication providing encrypted data transfers. For bitstream resilient SoC models the work extends a logic obfuscation module with runtime security leading to a secure assessment framework. This work explores the microarchitectural vulnerabilities with Machine Learning models and proposes a Transfer Learning technique based counterfeit detection scheme for supply chain vulnerability.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379453572Subjects--Topical Terms:

596380
Electrical engineering.
Subjects--Index Terms:

SoC designIndex Terms--Genre/Form:

554714
Electronic books.

A Secure SoC Platform for Security Assessments in FPGAs.
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502 $a Thesis (Ph.D.)--The University of North Carolina at Charlotte, 2023.
504 $a Includes bibliographical references
520 $a With the rapid increase in connected devices and SoC design architecture being used in diverse platforms, they become potential targets to gain unauthorized access for data and privacy invasion. Therefore, heterogeneous SoC architecture raises security concerns in addition to the benefits they offer with improved throughput. They are susceptible to side-channel attacks where secure information is extracted through communication channels. Crypto algorithms implemented for secure authentication tend to leak sensitive information jeopardizing system security. Memory corruption vulnerabilities, code injection, buffer overflow attacks and other software-based attacks through untrusted channels tend to control the flow of the application with malicious data. Though traditional defense mechanisms have been implemented they are all still vulnerable to side-channel attacks.Secure measures to protect the interfaces and data propagation through different channels are critical and building a resilient model consists of the on-chip security factors. In this work, a platform based SoC model is implemented to meet the security objectives using the RISC-V architecture in which an information flow tracking module tracks the flow of data for the system's integrity along with crypto engines and a secure boot mechanism for secure device authentication providing encrypted data transfers. For bitstream resilient SoC models the work extends a logic obfuscation module with runtime security leading to a secure assessment framework. This work explores the microarchitectural vulnerabilities with Machine Learning models and proposes a Transfer Learning technique based counterfeit detection scheme for supply chain vulnerability.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
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650 4 $a Computer engineering. $3 569006
653 $a SoC design
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653 $a Crypto alogorithms
653 $a RISC-V
653 $a Network security
653 $a FPGAs
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710 2 $a The University of North Carolina at Charlotte. $b Electrical Engineering. $3 1182889
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