國立虎尾科技大學 |

An FPGA Implementation of SipHash.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	An FPGA Implementation of SipHash./
Author:	Welte, Benjamin.
Description:	1 online resource (36 pages)
Notes:	Source: Masters Abstracts International, Volume: 84-12.
Contained By:	Masters Abstracts International84-12.
Subject:	Computer engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798379748227

An FPGA Implementation of SipHash.
Welte, Benjamin.

An FPGA Implementation of SipHash. - 1 online resource (36 pages)

Source: Masters Abstracts International, Volume: 84-12.

Thesis (M.S.)--Iowa State University, 2023.

Includes bibliographical references

Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, despite cryptographic hashing's security and error-correction capabilities, it can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture's throughput and acceleration vs. software were measured on Xilinx's Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can nearly reach 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798379748227Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

FPGA acceleratorIndex Terms--Genre/Form:

554714
Electronic books.

An FPGA Implementation of SipHash.
LDR:02697ntm a22003977 4500 001 1143551
005 20240517104557.5
006 m o d
007 cr mn ---uuuuu
008 250605s2023 xx obm 000 0 eng d
020 $a 9798379748227
035 $a (MiAaPQ)AAI29995373
035 $a AAI29995373
040 $a MiAaPQ $b eng $c MiAaPQ $d NTU
100 1 $a Welte, Benjamin. $3 1468272
245 1 3 $a An FPGA Implementation of SipHash.
264 0 $c 2023
300 $a 1 online resource (36 pages)
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
500 $a Source: Masters Abstracts International, Volume: 84-12.
500 $a Advisor: Zambreno, Joseph.
502 $a Thesis (M.S.)--Iowa State University, 2023.
504 $a Includes bibliographical references
520 $a Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, despite cryptographic hashing's security and error-correction capabilities, it can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture's throughput and acceleration vs. software were measured on Xilinx's Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can nearly reach 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2024
538 $a Mode of access: World Wide Web
650 4 $a Computer engineering. $3 569006
650 4 $a Computer science. $3 573171
650 4 $a Information technology. $3 559429
653 $a FPGA accelerator
653 $a Computer architecture
653 $a Hash function
653 $a DHTs
653 $a HMACs
655 7 $a Electronic books. $2 local $3 554714
690 $a 0464
690 $a 0984
690 $a 0489
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Iowa State University. $b Computer Engineering. $3 1468273
773 0 $t Masters Abstracts International $g 84-12.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=29995373 $z click for full text (PQDT)