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Efficient Algorithms, Hardware Architectures and Circuits for Deep Learning Accelerators.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Efficient Algorithms, Hardware Architectures and Circuits for Deep Learning Accelerators./
Author:	Wang, Miaorong.
Description:	1 online resource (138 pages)
Notes:	Source: Dissertations Abstracts International, Volume: 85-09, Section: B.
Contained By:	Dissertations Abstracts International85-09B.
Subject:	Computer engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9798381957211

Efficient Algorithms, Hardware Architectures and Circuits for Deep Learning Accelerators.
Wang, Miaorong.

Efficient Algorithms, Hardware Architectures and Circuits for Deep Learning Accelerators. - 1 online resource (138 pages)

Source: Dissertations Abstracts International, Volume: 85-09, Section: B.

Thesis (Ph.D.)--Massachusetts Institute of Technology, 2023.

Includes bibliographical references

Deep learning has permeated many industries due to its state-of-the-art ability to process complex data and uncover intricate patterns. However, it is computationally expensive. Researchers have shown in theory and practice that the progress of deep learning in many applications is heavily reliant on increases in computing power, and thus leads to increasing energy demand. That may impede further advancement in the field. To tackle that challenge, this thesis presents several techniques to improve the energy efficiency of deep learning accelerators while adhering to the accuracy and throughput requirements of the desired application.First, we develop hybrid dataflows and co-design the memory hierarchy. That enables designers to trade off the reuse between different data types across different storage elements provided by the technology for higher energy efficiency. Second, we propose a weight tuning algorithm and accelerator co-design, which optimizes the bit representation of weights for energy reduction. Last, we present VideoTime, an algorithm and accelerator co-design for efficient real-time video understanding with temporal redundancy reduction and temporal modeling. Our proposed techniques enrich accelerator designers' toolkits, pushing the boundaries of energy efficiency for sustainable advances in deep learning.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2024

Mode of access: World Wide Web

ISBN: 9798381957211Subjects--Topical Terms:

569006
Computer engineering.
Subjects--Index Terms:

Hardware architecturesIndex Terms--Genre/Form:

554714
Electronic books.

Efficient Algorithms, Hardware Architectures and Circuits for Deep Learning Accelerators.
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504 $a Includes bibliographical references
520 $a Deep learning has permeated many industries due to its state-of-the-art ability to process complex data and uncover intricate patterns. However, it is computationally expensive. Researchers have shown in theory and practice that the progress of deep learning in many applications is heavily reliant on increases in computing power, and thus leads to increasing energy demand. That may impede further advancement in the field. To tackle that challenge, this thesis presents several techniques to improve the energy efficiency of deep learning accelerators while adhering to the accuracy and throughput requirements of the desired application.First, we develop hybrid dataflows and co-design the memory hierarchy. That enables designers to trade off the reuse between different data types across different storage elements provided by the technology for higher energy efficiency. Second, we propose a weight tuning algorithm and accelerator co-design, which optimizes the bit representation of weights for energy reduction. Last, we present VideoTime, an algorithm and accelerator co-design for efficient real-time video understanding with temporal redundancy reduction and temporal modeling. Our proposed techniques enrich accelerator designers' toolkits, pushing the boundaries of energy efficiency for sustainable advances in deep learning.
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