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Multi-net optimization of VLSI inter...

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Multi-net optimization of VLSI interconnect

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Multi-net optimization of VLSI interconnect/ by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
Author:	Moiseev, Konstantin.
other author:	Kolodny, Avinoam.
Published:	New York, NY :Springer New York : : 2015.,
Description:	xvi, 233 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Interconnects (Integrated circuit technology) -
Online resource:	http://dx.doi.org/10.1007/978-1-4614-0821-5
ISBN:	9781461408215 (electronic bk.)

Multi-net optimization of VLSI interconnect
Moiseev, Konstantin.

Multi-net optimization of VLSI interconnect[electronic resource] /by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. - New York, NY :Springer New York :2015. - xvi, 233 p. :ill. (some col.), digital ;24 cm.

An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.

ISBN: 9781461408215 (electronic bk.)

Standard No.: 10.1007/978-1-4614-0821-5doiSubjects--Topical Terms:

655374
Interconnects (Integrated circuit technology)

LC Class. No.: TK7874.53

Dewey Class. No.: 621.3815

Multi-net optimization of VLSI interconnect
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245 1 0 $a Multi-net optimization of VLSI interconnect $h [electronic resource] / $c by Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer.
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300 $a xvi, 233 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a An Overview of the VLSI Interconnect Problem -- Interconnect Aspects in Design Methodology and EDA Tools -- Scaling Dependent Electrical Modeling of Interconnects -- Net-by-Net Wire Optimization -- Multi-Net Sizing and Spacing of Bundle Wires -- Multi-net Sizing and Spacing in General Layouts -- Interconnect Optimization by Net Ordering -- Layout Migration -- Future Directions in Interconnect Optimization.
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650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Processor Architectures. $3 669787
700 1 $a Kolodny, Avinoam. $3 1064099
700 1 $a Wimer, Shmuel. $3 1064100
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