國立虎尾科技大學 |

Analysis and design of networks-on-chip under high process variation

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Analysis and design of networks-on-chip under high process variation/ by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed.
Author:	Ezz-Eldin, Rabab.
other author:	El-Moursy, Magdy Ali.
Published:	Cham :Springer International Publishing : : 2015.,
Description:	xxi, 141 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Networks on a chip - Design. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-25766-2
ISBN:	9783319257662

Analysis and design of networks-on-chip under high process variation
Ezz-Eldin, Rabab.

Analysis and design of networks-on-chip under high process variation[electronic resource] /by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed. - Cham :Springer International Publishing :2015. - xxi, 141 p. :ill. (some col.), digital ;24 cm.

Introduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies; Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion.

ISBN: 9783319257662

Standard No.: 10.1007/978-3-319-25766-2doiSubjects--Topical Terms:

1019701
Networks on a chip
--Design.

LC Class. No.: TK5105.546

Dewey Class. No.: 006.22

Analysis and design of networks-on-chip under high process variation
LDR:02589nam a2200313 a 4500 001 838965
003 DE-He213
005 20160516114615.0
006 m d
007 cr nn 008maaau
008 160616s2015 gw s 0 eng d
020 $a 9783319257662 $q (electronic bk.)
020 $a 9783319257648 $q (paper)
024 7 $a 10.1007/978-3-319-25766-2 $2 doi
035 $a 978-3-319-25766-2
040 $a GP $c GP
041 0 $a eng
050 4 $a TK5105.546
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 006.22 $2 23
090 $a TK5105.546 $b .E99 2015
100 1 $a Ezz-Eldin, Rabab. $3 1070411
245 1 0 $a Analysis and design of networks-on-chip under high process variation $h [electronic resource] / $c by Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F.A. Hamed.
260 $a Cham : $c 2015. $b Springer International Publishing : $b Imprint: Springer,
300 $a xxi, 141 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Network On Chip Aspects -- Interconnection -- Process Variation -- Synchronous And Asynchronous NoC Design Under High Process Variation -- Novel Routing Algorithm -- Simulation Results -- Conclusions.
520 $a This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies; Includes an overview of the synchronous clocking scheme, clock distribution network, main building blocks in asynchronous NoC design, handshake protocols, data encoding, asynchronous protocol converters and routing algorithms; Describes a novel adaptive routing algorithm for asynchronous NoC designs, which selects the appr opriate output path based on process variation and congestion.
650 0 $a Networks on a chip $x Design. $3 1019701
650 0 $a Asynchronous circuits. $3 1069577
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Processor Architectures. $3 669787
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
700 1 $a El-Moursy, Magdy Ali. $3 1070412
700 1 $a Hamed, Hesham F.A. $3 1070413
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-25766-2
950 $a Engineering (Springer-11647)