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Microfluidic very large scale integr...
~
Pop, Paul.
Microfluidic very large scale integration (VLSI) = modeling, simulation, testing, compilation and physical synthesis /
Record Type:
Language materials, printed : Monograph/item
Title/Author:
Microfluidic very large scale integration (VLSI)/ by Paul Pop, Wajid Hassan Minhass, Jan Madsen.
Reminder of title:
modeling, simulation, testing, compilation and physical synthesis /
Author:
Pop, Paul.
other author:
Minhass, Wajid Hassan.
Published:
Cham :Springer International Publishing : : 2016.,
Description:
xv, 270 p. :ill., digital ; : 24 cm.;
Contained By:
Springer eBooks
Subject:
Integrated circuits - Very large scale integration. -
Online resource:
http://dx.doi.org/10.1007/978-3-319-29599-2
ISBN:
9783319295992
Microfluidic very large scale integration (VLSI) = modeling, simulation, testing, compilation and physical synthesis /
Pop, Paul.
Microfluidic very large scale integration (VLSI)
modeling, simulation, testing, compilation and physical synthesis /[electronic resource] :by Paul Pop, Wajid Hassan Minhass, Jan Madsen. - Cham :Springer International Publishing :2016. - xv, 270 p. :ill., digital ;24 cm.
Introduction -- Part 1. Preliminaries -- Design Methodology for Flow-based Microfluidic Biochips -- Biochip Architecture Model -- Biochemical Application Modeling -- Part 2. Compilation -- Compiling High-Level Languages -- Application Mapping and Simulation -- Control Synthesis and Pin-Count Minimization -- Part 3. Physical Design -- Allocation and Schematic Design -- Placement and Routing -- On-Chip Control Synthesis -- Testing and Fault-Tolerant Design.
ISBN: 9783319295992
Standard No.: 10.1007/978-3-319-29599-2doiSubjects--Topical Terms:
563475
Integrated circuits
--Very large scale integration.
LC Class. No.: TK7874.7
Dewey Class. No.: 621.395
Microfluidic very large scale integration (VLSI) = modeling, simulation, testing, compilation and physical synthesis /
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Introduction -- Part 1. Preliminaries -- Design Methodology for Flow-based Microfluidic Biochips -- Biochip Architecture Model -- Biochemical Application Modeling -- Part 2. Compilation -- Compiling High-Level Languages -- Application Mapping and Simulation -- Control Synthesis and Pin-Count Minimization -- Part 3. Physical Design -- Allocation and Schematic Design -- Placement and Routing -- On-Chip Control Synthesis -- Testing and Fault-Tolerant Design.
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Engineering (Springer-11647)
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