國立虎尾科技大學 |

Memory controllers for mixed-time-criticality systems = architectures, methodologies and trade-offs /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Memory controllers for mixed-time-criticality systems/ by Sven Goossens ... [et al.].
Reminder of title:	architectures, methodologies and trade-offs /
other author:	Goossens, Sven.
Published:	Cham :Springer International Publishing : : 2016.,
Description:	xxvii, 202 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Embedded computer systems - Programming. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-32094-6
ISBN:	9783319320946

Memory controllers for mixed-time-criticality systems = architectures, methodologies and trade-offs /
Memory controllers for mixed-time-criticality systemsarchitectures, methodologies and trade-offs /[electronic resource] :by Sven Goossens ... [et al.]. - Cham :Springer International Publishing :2016. - xxvii, 202 p. :ill., digital ;24 cm. - Embedded systems,2193-0155. - Embedded systems..

Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

ISBN: 9783319320946

Standard No.: 10.1007/978-3-319-32094-6doiSubjects--Topical Terms:

567087
Embedded computer systems
--Programming.

LC Class. No.: TK7895.E42

Dewey Class. No.: 006.22

Memory controllers for mixed-time-criticality systems = architectures, methodologies and trade-offs /
LDR:02084nam a2200325 a 4500 001 863685
003 DE-He213
005 20161013103049.0
006 m d
007 cr nn 008maaau
008 170720s2016 gw s 0 eng d
020 $a 9783319320946 $q (electronic bk.)
020 $a 9783319320939 $q (paper)
024 7 $a 10.1007/978-3-319-32094-6 $2 doi
035 $a 978-3-319-32094-6
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.E42
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 006.22 $2 23
090 $a TK7895.E42 $b M533 2016
245 0 0 $a Memory controllers for mixed-time-criticality systems $h [electronic resource] : $b architectures, methodologies and trade-offs / $c by Sven Goossens ... [et al.].
260 $a Cham : $c 2016. $b Springer International Publishing : $b Imprint: Springer,
300 $a xxvii, 202 p. : $b ill., digital ; $c 24 cm.
490 1 $a Embedded systems, $x 2193-0155
505 0 $a Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.
520 $a This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
650 0 $a Embedded computer systems $x Programming. $3 567087
650 0 $a Dynamic random access memory. $3 1107897
650 0 $a Programmable controllers. $3 563480
650 0 $a Real-time data processing. $3 568181
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Processor Architectures. $3 669787
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
700 1 $a Goossens, Sven. $3 1107896
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
830 0 $a Embedded systems. $3 1022145
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-32094-6
950 $a Engineering (Springer-11647)