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Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information./
Author:	Oh, Taehwan.
Description:	1 online resource (104 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.
Contained By:	Dissertation Abstracts International75-01B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781303492433

Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information.
Oh, Taehwan.

Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information. - 1 online resource (104 pages)

Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

This item is not available from ProQuest Dissertations & Theses.

As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781303492433Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information.
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100 1 $a Oh, Taehwan. $3 1184199
245 1 0 $a Power Efficient Analog-to-Digital Converters using Both Voltage and Time Domain Information.
264 0 $c 2013
300 $a 1 online resource (104 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 75-01(E), Section: B.
500 $a Adviser: Un-Ku Moon.
502 $a Thesis (Ph.D.) $c Oregon State University $d 2013.
504 $a Includes bibliographical references
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information.
520 $a As a first approach, a new DeltaSigma ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed DeltaSigma ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b quantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13microm CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency.
520 $a To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13microm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a Oregon State University. $b Electrical Engineering. $3 1184200
773 0 $t Dissertation Abstracts International $g 75-01B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3574326 $z click for full text (PQDT)