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Comparator power reduction for low power successive approximation analog to digital converters.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Comparator power reduction for low power successive approximation analog to digital converters./
Author:	Ahmadi, Muhammad.
Description:	1 online resource (86 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 76-12(E), Section: B.
Contained By:	Dissertation Abstracts International76-12B(E).
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781321996371

Comparator power reduction for low power successive approximation analog to digital converters.
Ahmadi, Muhammad.

Comparator power reduction for low power successive approximation analog to digital converters. - 1 online resource (86 pages)

Source: Dissertation Abstracts International, Volume: 76-12(E), Section: B.

Thesis (Ph.D.)

Includes bibliographical references

This item is not available from ProQuest Dissertations & Theses.

Many applications like sensor nodes, wireless communications and consumer products require analog-to-digital converters (ADCs) to digitize the analog information. Charge redistribution successive approximation register (SAR) ADC has been a popular candidate in these applications due to its simplicity, low power consumption, medium speed and resolution. The three primary components of a SAR ADC are the digital-to-analog converter (DAC), digital SAR logic, and comparator. The power consumption of the DAC can be greatly minimized by employing a small unit capacitor and digital circuits benefit from technology scaling. Consequently, the comparator has become a major source of power consumption in recent power efficient SAR ADCs.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781321996371Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Comparator power reduction for low power successive approximation analog to digital converters.
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100 1 $a Ahmadi, Muhammad. $3 1184292
245 1 0 $a Comparator power reduction for low power successive approximation analog to digital converters.
264 0 $c 2015
300 $a 1 online resource (86 pages)
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337 $a computer $b c $2 rdamedia
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500 $a Source: Dissertation Abstracts International, Volume: 76-12(E), Section: B.
500 $a Adviser: Won Namgoong.
502 $a Thesis (Ph.D.) $c The University of Texas at Dallas $d 2015.
504 $a Includes bibliographical references
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a Many applications like sensor nodes, wireless communications and consumer products require analog-to-digital converters (ADCs) to digitize the analog information. Charge redistribution successive approximation register (SAR) ADC has been a popular candidate in these applications due to its simplicity, low power consumption, medium speed and resolution. The three primary components of a SAR ADC are the digital-to-analog converter (DAC), digital SAR logic, and comparator. The power consumption of the DAC can be greatly minimized by employing a small unit capacitor and digital circuits benefit from technology scaling. Consequently, the comparator has become a major source of power consumption in recent power efficient SAR ADCs.
520 $a Two comparator power reduction techniques are proposed which are based on the observation that the comparator noise variance need not be the same for each bit cycle of the SAR ADC. So, the performance of the SAR ADC is analyzed rigorously assuming that the comparator thermal noise differs for each bit cycle. The mathematical model suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary.
520 $a As a first technique, a noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step by changing the number of votes taken at each bit step. As a proof of concept, a 10b SAR ADC that operates at 0.5 V supply voltage and supports a flexible differential input dynamic range from 0.4 V to 1 V has been fabricated in 65nm CMOS process.
520 $a Second, the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels are theoretically analyzed. Simulation results show that up to 50% and 60% reduction in comparator power consumption for 10b and 12b SAR ADCs, respectively, can be achieved. To reduce the implementation complexity, the comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators are sufficient to achieve near ideal performance.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a The University of Texas at Dallas. $b Electrical Engineering. $3 1181534
773 0 $t Dissertation Abstracts International $g 76-12B(E).
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3719312 $z click for full text (PQDT)