國立虎尾科技大學 |

Low-cost assertion-based fault tolerance in hardware and software.

Record Type:	Language materials, manuscript : Monograph/item
Title/Author:	Low-cost assertion-based fault tolerance in hardware and software./
Author:	Vemu, Ramtilak.
Description:	1 online resource (166 pages)
Notes:	Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 5780.
Contained By:	Dissertation Abstracts International70-01B.
Subject:	Electrical engineering. -
Online resource:	click for full text (PQDT)
ISBN:	9781109007237

Low-cost assertion-based fault tolerance in hardware and software.
Vemu, Ramtilak.

Low-cost assertion-based fault tolerance in hardware and software. - 1 online resource (166 pages)

Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 5780.

Thesis (Ph.D.)--The University of Texas at Austin, 2008.

Includes bibliographical references

In the recent past, there has been an increasing demand for low-cost safety critical applications. Custom-off-the-shelf (COTS) processors are preferred for usage in these applications due to their low cost. The reliability provided by these processors, however, is not sufficient to meet the safety requirements of these applications. Furthermore, due to the trends followed by the processor industry to enhance the performance of processors, the reliability provided by these processors is projected to decrease in the future. Traditional techniques for enhancing the reliability of computer systems are not viable for these applications due to the high overheads (and hence cost) incurred by them. This thesis describes fault tolerance techniques tailored for these applications, adhering to the tight overhead constraints in the area, memory, and performance dimensions. Techniques at both the hardware level (to be used by the processor manufacturers) and the software level (to be used by the application developers) are presented.

Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018

Mode of access: World Wide Web

ISBN: 9781109007237Subjects--Topical Terms:

596380
Electrical engineering.
Index Terms--Genre/Form:

554714
Electronic books.

Low-cost assertion-based fault tolerance in hardware and software.
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245 1 0 $a Low-cost assertion-based fault tolerance in hardware and software.
264 0 $c 2008
300 $a 1 online resource (166 pages)
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500 $a Source: Dissertation Abstracts International, Volume: 70-01, Section: B, page: 5780.
500 $a Adviser: Jacob A. Abraham.
502 $a Thesis (Ph.D.)--The University of Texas at Austin, 2008.
504 $a Includes bibliographical references
520 $a In the recent past, there has been an increasing demand for low-cost safety critical applications. Custom-off-the-shelf (COTS) processors are preferred for usage in these applications due to their low cost. The reliability provided by these processors, however, is not sufficient to meet the safety requirements of these applications. Furthermore, due to the trends followed by the processor industry to enhance the performance of processors, the reliability provided by these processors is projected to decrease in the future. Traditional techniques for enhancing the reliability of computer systems are not viable for these applications due to the high overheads (and hence cost) incurred by them. This thesis describes fault tolerance techniques tailored for these applications, adhering to the tight overhead constraints in the area, memory, and performance dimensions. Techniques at both the hardware level (to be used by the processor manufacturers) and the software level (to be used by the application developers) are presented.
520 $a At the hardware level, this thesis presents a technique for detecting faults in the processor control logic, for which techniques proposed previously incur very high overheads. Rather than detect all modeled faults, the technique protects against a subset of faults such that the best possible overall protection is achieved while incurring only permissible overheads. This subset of faults is selected depending on the probability of each individual fault causing damage to the architectural state of the processor and the overhead incurred in protecting against the fault. The technique is validated on control logic modules of an industrial processor.
520 $a At the software level, this thesis concentrates on a category of errors called control flow errors. We describe an error detection technique which incurs lower overheads than any of the previously proposed techniques while at the same time detecting more errors than all of them. Even these low overheads may be too restrictive for some applications. For such applications, we present a technique for providing the best error detection capability possible at the overheads allowed. Once an error is detected, error recovery actions need to be performed. In this thesis, we present an error correction technique which automatically performs error recovery with a very low latency. The technique reuses the information available from the error detection technique to perform the recovery and hence, does not incur any additional performance penalty. All the techniques proposed at the software level have been integrated with GCC, a commonly used software compiler. This permits the fault tolerance to be incorporated into the application automatically as part of the compilation process itself. Evaluations are performed on SPEC and MiBench benchmark programs using an in-house software error injection framework.
533 $a Electronic reproduction. $b Ann Arbor, Mich. : $c ProQuest, $d 2018
538 $a Mode of access: World Wide Web
650 4 $a Electrical engineering. $3 596380
650 4 $a Computer science. $3 573171
655 7 $a Electronic books. $2 local $3 554714
690 $a 0544
690 $a 0984
710 2 $a ProQuest Information and Learning Co. $3 1178819
710 2 $a The University of Texas at Austin. $b Electrical Engineering. $3 1189553
773 0 $t Dissertation Abstracts International $g 70-01B.
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3344358 $z click for full text (PQDT)