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Scalar-Vector GPU Architectures.
~
Northeastern University.
Scalar-Vector GPU Architectures.
Record Type:
Language materials, manuscript : Monograph/item
Title/Author:
Scalar-Vector GPU Architectures./
Author:
Chen, Zhongliang.
Description:
1 online resource (70 pages)
Notes:
Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
Contained By:
Dissertation Abstracts International78-10B(E).
Subject:
Computer engineering. -
Online resource:
click for full text (PQDT)
ISBN:
9781369806373
Scalar-Vector GPU Architectures.
Chen, Zhongliang.
Scalar-Vector GPU Architectures.
- 1 online resource (70 pages)
Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
Thesis (Ph.D.)--Northeastern University, 2017.
Includes bibliographical references
Graphics Processing Units (GPUs) have evolved to become high throughput processors for general purpose data-parallel applications. Most GPU execution exploits a Single Instruction Multiple Data (SIMD) model, where a single operation is performed on multiple data at a time. However, neither runtime or hardware pays attention to whether the data components on SIMD lanes are the same or different. When a SIMD unit operates on multiple copies of the same data, redundant computations are generated. The inefficient execution can degrade performance and deteriorate power efficiency.
Electronic reproduction.
Ann Arbor, Mich. :
ProQuest,
2018
Mode of access: World Wide Web
ISBN: 9781369806373Subjects--Topical Terms:
569006
Computer engineering.
Index Terms--Genre/Form:
554714
Electronic books.
Scalar-Vector GPU Architectures.
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Source: Dissertation Abstracts International, Volume: 78-10(E), Section: B.
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Adviser: David Kaeli.
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Thesis (Ph.D.)--Northeastern University, 2017.
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Includes bibliographical references
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Graphics Processing Units (GPUs) have evolved to become high throughput processors for general purpose data-parallel applications. Most GPU execution exploits a Single Instruction Multiple Data (SIMD) model, where a single operation is performed on multiple data at a time. However, neither runtime or hardware pays attention to whether the data components on SIMD lanes are the same or different. When a SIMD unit operates on multiple copies of the same data, redundant computations are generated. The inefficient execution can degrade performance and deteriorate power efficiency.
520
$a
A significant number of SIMD instructions in GPU compute programs demonstrate scalar characteristics, i.e., they operate on the same data across their active lanes. Treating them as normal SIMD instructions results in inefficient GPU execution. To better serve both scalar and vector operations, we propose a heterogeneous scalar-vector GPU architecture. In this thesis we propose the design of a specialized scalar pipeline to handle scalar instructions efficiently with only a single copy of the data, freeing the SIMD pipeline for normal vector execution. The proposed architecture provides an opportunity to save power by just broadcasting the results of a single computation to multiple outputs. In order to balance scalar and vector units, we propose novel schemes to efficiently resolve scalar-vector data dependencies, schedule warps, and dispatch instructions. Also, we consider the impact of varying warp sizes on our scalar-vector architecture and explore subwarp execution for power efficiency. Finally, we demonstrate that the interconnect and memory subsystem can be the new limiting factor on scalar-vector execution.
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ProQuest,
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2018
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Mode of access: World Wide Web
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Computer engineering.
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Northeastern University.
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78-10B(E).
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click for full text (PQDT)
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