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Parasitic substrate coupling in high voltage integrated circuits = minority and majority carriers propagation in semiconductor substrate /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Parasitic substrate coupling in high voltage integrated circuits/ by Pietro Buccella ... [et al.].
Reminder of title:	minority and majority carriers propagation in semiconductor substrate /
other author:	Buccella, Pietro.
Published:	Cham :Springer International Publishing : : 2018.,
Description:	xvii, 183 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Engineering. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-74382-0
ISBN:	9783319743820

Parasitic substrate coupling in high voltage integrated circuits = minority and majority carriers propagation in semiconductor substrate /
Parasitic substrate coupling in high voltage integrated circuitsminority and majority carriers propagation in semiconductor substrate /[electronic resource] :by Pietro Buccella ... [et al.]. - Cham :Springer International Publishing :2018. - xvii, 183 p. :ill., digital ;24 cm. - Analog circuits and signal processing,1872-082X. - Analog circuits and signal processing..

Chapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections.

ISBN: 9783319743820

Standard No.: 10.1007/978-3-319-74382-0doiSubjects--Topical Terms:

561152
Engineering.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Parasitic substrate coupling in high voltage integrated circuits = minority and majority carriers propagation in semiconductor substrate /
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505 0 $a Chapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.
520 $a This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections.
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