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Designing with Xilinx FPGAs = using ...

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Designing with Xilinx FPGAs = using Vivado /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Designing with Xilinx FPGAs/ edited by Sanjay Churiwala.
Reminder of title:	using Vivado /
other author:	Churiwala, Sanjay.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	x, 260 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
Subject:	Field programmable gate arrays. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-42438-5
ISBN:	9783319424385

Designing with Xilinx FPGAs = using Vivado /
Designing with Xilinx FPGAsusing Vivado /[electronic resource] :edited by Sanjay Churiwala. - Cham :Springer International Publishing :2017. - x, 260 p. :ill., digital ;24 cm.

State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.

ISBN: 9783319424385

Standard No.: 10.1007/978-3-319-42438-5doiSubjects--Uniform Titles:

Vivado Design Suite.
Subjects--Topical Terms:

564014
Field programmable gate arrays.

LC Class. No.: TK7895.G36 / D47 2017

Dewey Class. No.: 621.395

Designing with Xilinx FPGAs = using Vivado /
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245 0 0 $a Designing with Xilinx FPGAs $h [electronic resource] : $b using Vivado / $c edited by Sanjay Churiwala.
260 $a Cham : $c 2017. $b Springer International Publishing : $b Imprint: Springer,
300 $a x, 260 p. : $b ill., digital ; $c 24 cm.
505 0 $a State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
630 0 0 $a Vivado Design Suite. $3 1248079
650 0 $a Field programmable gate arrays. $3 564014
650 0 $a Computer-aided design. $3 528070
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Processor Architectures. $3 669787
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
700 1 $a Churiwala, Sanjay. $3 787907
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-42438-5
950 $a Engineering (Springer-11647)

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