Kawecka, Elżbieta.
Overview
| Works: | 0 works in 0 publications in 0 languages | |
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Titles
Logic Synthesis for VLSI-Based Combined Finite State Machines = Synthesis Targeting ASICs, CPLDs and FPGAs /
by:
Mazurkiewicz, Małgorzata.; Barkalov, Alexander.; Kawecka, Elżbieta.; SpringerLink (Online service); Mielcarek, Kamil.; Titarenko, Larysa.
(Language materials, printed)
, [http://id.loc.gov/vocabulary/relators/aut]