Zilic, Zeljko.
Overview
| Works: | 1 works in 0 publications in 0 languages | |
|---|---|---|
Titles
Verification by error modeling : = using testing techniques in hardware verification
by:
Zilic, Zeljko.; Radecka, Katarzyna.; SpringerLink (Online service)
(Language materials, printed)
Generating Hardware Assertion Checkers = For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
by:
Boule, Marc.; Zilic, Zeljko.; SpringerLink (Online service)
(Language materials, printed)
Accelerating test, validation and debug of high speed serial interfaces
by:
SpringerLink (Online service); Fan, Yongquan.; Zilic, Zeljko.
(Language materials, printed)
Subjects
Electronics and Microelectronics, Instrumentation.
Integrated circuits
Software Engineering/Programming and Operating Systems.
Error analysis (Mathematics)
Circuits and Systems.
System Performance and Evaluation.
Online data processing.
Interface circuits
Very high speed integrated circuits
Engineering.
Programming Languages, Compilers, Interpreters.