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Verification by error modeling : = u...

Radecka, Katarzyna.

Verification by error modeling : = using testing techniques in hardware verification

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Verification by error modeling :/ written by Katarzyna Radecka, Zeljko Zilic.
其他題名:	using testing techniques in hardware verification
作者:	Radecka, Katarzyna.
其他作者:	Zilic, Zeljko.
出版者:	Boston :Springer Science + Business Media, Inc., : c2004.,
面頁冊數:	xiv, 216 p. :ill., digital ; : 25 cm.;
叢書名:	Frontiers in electronic testing ;
Contained By:	Springer e-books
標題:	Integrated circuits - Very large scale integration -
電子資源:	http://dx.doi.org/10.1007/b105974
ISBN:	9780306487392 (electronic bk.)

Verification by error modeling : = using testing techniques in hardware verification
Radecka, Katarzyna.

Verification by error modeling :using testing techniques in hardware verification[electronic resource] /written by Katarzyna Radecka, Zeljko Zilic. - Boston :Springer Science + Business Media, Inc.,c2004. - xiv, 216 p. :ill., digital ;25 cm. - Frontiers in electronic testing ;25.

ISBN: 9780306487392 (electronic bk.)Subjects--Topical Terms:

682287
Integrated circuits
--Very large scale integration

LC Class. No.: TK7874.75 / .R33 2004

Dewey Class. No.: 621.395

Verification by error modeling : = using testing techniques in hardware verification
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