Zilic, Zeljko.
概要
| 作品: | 1 作品在 0 項出版品 0 種語言 | |
|---|---|---|
書目資訊
Verification by error modeling : = using testing techniques in hardware verification
by:
Zilic, Zeljko.; Radecka, Katarzyna.; SpringerLink (Online service)
(書目-語言資料,印刷品)
Generating Hardware Assertion Checkers = For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
by:
Boule, Marc.; Zilic, Zeljko.; SpringerLink (Online service)
(書目-語言資料,印刷品)
Accelerating test, validation and debug of high speed serial interfaces
by:
SpringerLink (Online service); Fan, Yongquan.; Zilic, Zeljko.
(書目-語言資料,印刷品)
主題
Electronics and Microelectronics, Instrumentation.
Integrated circuits
Software Engineering/Programming and Operating Systems.
Error analysis (Mathematics)
Circuits and Systems.
System Performance and Evaluation.
Online data processing.
Interface circuits
Very high speed integrated circuits
Engineering.
Programming Languages, Compilers, Interpreters.