國立虎尾科技大學 |

Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Advanced HDL Synthesis and SOC Prototyping / by Vaibbhav Taraate.
其他題名:	RTL Design Using Verilog /
作者:	Taraate, Vaibbhav.
面頁冊數:	XXI, 307 p. 263 illus., 196 illus. in color.online resource. :
Contained By:	Springer Nature eBook
標題:	Electronic circuits. -
電子資源:	https://doi.org/10.1007/978-981-10-8776-9
ISBN:	9789811087769

Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /
Taraate, Vaibbhav.

Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /[electronic resource] :by Vaibbhav Taraate. - 1st ed. 2019. - XXI, 307 p. 263 illus., 196 illus. in color.online resource.

Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

ISBN: 9789811087769

Standard No.: 10.1007/978-981-10-8776-9doiSubjects--Topical Terms:

563332
Electronic circuits.

LC Class. No.: TK7888.4

Dewey Class. No.: 621.3815

Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog /
LDR:02662nam a22003855i 4500 001 1010301
003 DE-He213
005 20200704161537.0
007 cr nn 008mamaa
008 210106s2019 si | s |||| 0|eng d
020 $a 9789811087769 $9 978-981-10-8776-9
024 7 $a 10.1007/978-981-10-8776-9 $2 doi
035 $a 978-981-10-8776-9
050 4 $a TK7888.4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
100 1 $a Taraate, Vaibbhav. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1109142
245 1 0 $a Advanced HDL Synthesis and SOC Prototyping $h [electronic resource] : $b RTL Design Using Verilog / $c by Vaibbhav Taraate.
250 $a 1st ed. 2019.
264 1 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2019.
300 $a XXI, 307 p. 263 illus., 196 illus. in color. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
505 0 $a Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520 $a This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
650 0 $a Electronic circuits. $3 563332
650 0 $a Microprogramming . $3 1257366
650 0 $a Logic design. $3 561473
650 1 4 $a Circuits and Systems. $3 670901
650 2 4 $a Control Structures and Microprogramming. $3 669788
650 2 4 $a Logic Design. $3 670915
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9789811087752
776 0 8 $i Printed edition: $z 9789811087776
856 4 0 $u https://doi.org/10.1007/978-981-10-8776-9
912 $a ZDB-2-ENG
912 $a ZDB-2-SXE
950 $a Engineering (SpringerNature-11647)
950 $a Engineering (R0) (SpringerNature-43712)