國立虎尾科技大學 |

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond/ by Guilei Wang.
作者:	Wang, Guilei.
面頁冊數:	XVI, 115 p.online resource. :
Contained By:	Springer Nature eBook
標題:	Semiconductors. -
電子資源:	https://doi.org/10.1007/978-981-15-0046-6
ISBN:	9789811500466

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond
Wang, Guilei.

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond[electronic resource] /by Guilei Wang. - 1st ed. 2019. - XVI, 115 p.online resource. - Springer Theses, Recognizing Outstanding Ph.D. Research,2190-5053. - Springer Theses, Recognizing Outstanding Ph.D. Research,.

Introduction -- Strain technology of Si-based materials -- SiGe Epitaxial Growth and material characterization -- SiGe Source and Drain Integration and transistor performance investigation -- Pattern Dependency behavior of SiGe Selective Epitaxy -- Summary and final words.

This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.

ISBN: 9789811500466

Standard No.: 10.1007/978-981-15-0046-6doiSubjects--Topical Terms:

578843
Semiconductors.

LC Class. No.: QC610.9-611.8

Dewey Class. No.: 537.622

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond
LDR:02843nam a22004095i 4500 001 1012391
003 DE-He213
005 20200706042247.0
007 cr nn 008mamaa
008 210106s2019 si | s |||| 0|eng d
020 $a 9789811500466 $9 978-981-15-0046-6
024 7 $a 10.1007/978-981-15-0046-6 $2 doi
035 $a 978-981-15-0046-6
050 4 $a QC610.9-611.8
072 7 $a TJFD5 $2 bicssc
072 7 $a TEC008090 $2 bisacsh
072 7 $a TJFD $2 thema
082 0 4 $a 537.622 $2 23
100 1 $a Wang, Guilei. $e author. $4 aut $4 http://id.loc.gov/vocabulary/relators/aut $3 1306638
245 1 0 $a Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond $h [electronic resource] / $c by Guilei Wang.
250 $a 1st ed. 2019.
264 1 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2019.
300 $a XVI, 115 p. $b online resource.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
347 $a text file $b PDF $2 rda
490 1 $a Springer Theses, Recognizing Outstanding Ph.D. Research, $x 2190-5053
505 0 $a Introduction -- Strain technology of Si-based materials -- SiGe Epitaxial Growth and material characterization -- SiGe Source and Drain Integration and transistor performance investigation -- Pattern Dependency behavior of SiGe Selective Epitaxy -- Summary and final words.
520 $a This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.
650 0 $a Semiconductors. $3 578843
650 0 $a Electronic circuits. $3 563332
650 0 $a Nanotechnology. $3 557660
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Nanotechnology and Microengineering. $3 722030
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer Nature eBook
776 0 8 $i Printed edition: $z 9789811500459
776 0 8 $i Printed edition: $z 9789811500473
776 0 8 $i Printed edition: $z 9789811500480
830 0 $a Springer Theses, Recognizing Outstanding Ph.D. Research, $x 2190-5053 $3 1253569
856 4 0 $u https://doi.org/10.1007/978-981-15-0046-6
912 $a ZDB-2-PHA
912 $a ZDB-2-SXP
950 $a Physics and Astronomy (SpringerNature-11651)
950 $a Physics and Astronomy (R0) (SpringerNature-43715)