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SystemVerilog for hardware descripti...

Taraate, Vaibbhav.

SystemVerilog for hardware description : = RTL design and verification /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	SystemVerilog for hardware description :/ Vaibbhav Taraate.
其他題名:	RTL design and verification /
其他題名:	RTL design and verification
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer, : 2020.,
面頁冊數:	xxi, 252 p. :col. ill. ; : 25 cm.;
標題:	SystemVerilog (Computer hardware description language) -
ISBN:	9789811544040 (hbk.) :

SystemVerilog for hardware description : = RTL design and verification /
Taraate, Vaibbhav.

SystemVerilog for hardware description :RTL design and verification /RTL design and verificationVaibbhav Taraate. - Singapore :Springer,2020. - xxi, 252 p. :col. ill. ;25 cm.

Includes bibliographical references.

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

ISBN: 9789811544040 (hbk.) :NT3943 Subjects--Topical Terms:

1027537
SystemVerilog (Computer hardware description language)

LC Class. No.: TK7885.7

Dewey Class. No.: 621.39/2

SystemVerilog for hardware description : = RTL design and verification /
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020 $a 9811544042 (hbk.)
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020 $z 9811544050 (ebk.)
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035 $a 1158279720
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050 # 4 $a TK7885.7
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100 1 $a Taraate, Vaibbhav. $3 1109142
245 1 0 $a SystemVerilog for hardware description : $b RTL design and verification / $c Vaibbhav Taraate.
246 3 0 $a RTL design and verification
260 # $a Singapore : $b Springer, $c 2020.
300 $a xxi, 252 p. : $b col. ill. ; $c 25 cm.
504 $a Includes bibliographical references.
520 # $a This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
650 # 0 $a SystemVerilog (Computer hardware description language) $3 1027537