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ASIC design and synthesis : = RTL de...

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Taraate, Vaibbhav.

ASIC design and synthesis : = RTL design using Verilog /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	ASIC design and synthesis :/ Vaibbhav Taraate.
其他題名:	RTL design using Verilog /
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer, : c2021.,
面頁冊數:	xxi, 330 p. :ill. (chiefly col.) ; : 24 cm.;
標題:	Logic design. -
ISBN:	9789813346413 (cloth) :

ASIC design and synthesis : = RTL design using Verilog /
Taraate, Vaibbhav.

ASIC design and synthesis :RTL design using Verilog /Vaibbhav Taraate. - Singapore :Springer,c2021. - xxi, 330 p. :ill. (chiefly col.) ;24 cm.

Includes bibliographical references and index.

ISBN: 9789813346413 (cloth) :NT5065Subjects--Topical Terms:

561473
Logic design.

LC Class. No.: TK7874.6

Dewey Class. No.: 621.3815

ASIC design and synthesis : = RTL design using Verilog /
LDR:00649cam a2200205 a 450 001 1059965
003 OCoLC
005 20220329024657.0
008 220507s2021 si a b 001 0 eng d
020 $a 9789813346413 (cloth) : $c NT5065
020 $z 9789813346420 (ebook)
035 $a (OCoLC)1202752318
035 $a on1202752318
040 $a YDX $b eng $c NFU $d DKU $d OCLCO $d OCLCF
041 0 # $a eng
050 # 4 $a TK7874.6
082 0 4 $a 621.3815 $2 23
100 1 $a Taraate, Vaibbhav. $3 1109142
245 1 0 $a ASIC design and synthesis : $b RTL design using Verilog / $c Vaibbhav Taraate.
260 # $a Singapore : $b Springer, $c c2021.
300 $a xxi, 330 p. : $b ill. (chiefly col.) ; $c 24 cm.
504 $a Includes bibliographical references and index.
650 # 0 $a Logic design. $3 561473
650 # 0 $a Microprogramming. $3 1022170
650 # 0 $a Electronic circuits. $3 563332
650 # 0 $a Verilog (Computer hardware description language) $3 563915
650 # 0 $a Application-specific integrated circuits $x Design. $3 1250579

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