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CMOS SRAM circuit design and paramet...

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CMOS SRAM circuit design and parametric test in nano-scaled technologies = process-aware SRAM design and test /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	CMOS SRAM circuit design and parametric test in nano-scaled technologies/ by Andrei Pavlov, Manoj Sachdev.
Reminder of title:	process-aware SRAM design and test /
Author:	Pavlov, Andrei.
other author:	Sachdev, Manoj.
Published:	Dordrecht :Springer Science + Business Media B.V, : 2008.,
Description:	212 p. :ill., digital ; : 24 cm.;
Series:	Frontiers in electronic testing ;
Contained By:	Springer eBooks
Subject:	Memory Structures. -
Online resource:	http://dx.doi.org/10.1007/978-1-4020-8363-1
ISBN:	9781402083631 (electronic bk.)

CMOS SRAM circuit design and parametric test in nano-scaled technologies = process-aware SRAM design and test /
Pavlov, Andrei.

CMOS SRAM circuit design and parametric test in nano-scaled technologiesprocess-aware SRAM design and test /[electronic resource] :by Andrei Pavlov, Manoj Sachdev. - Dordrecht :Springer Science + Business Media B.V,2008. - 212 p. :ill., digital ;24 cm. - Frontiers in electronic testing ;40.

ISBN: 9781402083631 (electronic bk.)Subjects--Topical Terms:

677022
Memory Structures.

Dewey Class. No.: 621.38152

CMOS SRAM circuit design and parametric test in nano-scaled technologies = process-aware SRAM design and test /
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245 1 0 $a CMOS SRAM circuit design and parametric test in nano-scaled technologies $h [electronic resource] : $b process-aware SRAM design and test / $c by Andrei Pavlov, Manoj Sachdev.
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