國立虎尾科技大學 |

CMOS test and evaluation = a physical perspective /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	CMOS test and evaluation/ by Manjul Bhushan, Mark B. Ketchen.
其他題名:	a physical perspective /
作者:	Bhushan, Manjul.
其他作者:	Ketchen, Mark B.
出版者:	New York, NY :Springer New York : : 2015.,
面頁冊數:	xiii, 424 p. :ill., digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	System safety. -
電子資源:	http://dx.doi.org/10.1007/978-1-4939-1349-7
ISBN:	9781493913497 (electronic bk.)

CMOS test and evaluation = a physical perspective /
Bhushan, Manjul.

CMOS test and evaluationa physical perspective /[electronic resource] :by Manjul Bhushan, Mark B. Ketchen. - New York, NY :Springer New York :2015. - xiii, 424 p. :ill., digital ;24 cm.

Introduction -- CMOS Circuit Basics -- CMOS Storage Elements and Synchronous Logic -- IDDQ and Power -- Embedded PVT Monitors -- Variability -- Product Chip Test and Characterization -- Reliability, Burn-In and Guardbands -- Data Analysis and Characterization -- CMOS Metrics and Model Evaluation.

This book extends test structure applications described in Microelectronic Test Structures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

ISBN: 9781493913497 (electronic bk.)

Standard No.: 10.1007/978-1-4939-1349-7doiSubjects--Topical Terms:

639363
System safety.

LC Class. No.: TK7874

Dewey Class. No.: 621.381

CMOS test and evaluation = a physical perspective /
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505 0 $a Introduction -- CMOS Circuit Basics -- CMOS Storage Elements and Synchronous Logic -- IDDQ and Power -- Embedded PVT Monitors -- Variability -- Product Chip Test and Characterization -- Reliability, Burn-In and Guardbands -- Data Analysis and Characterization -- CMOS Metrics and Model Evaluation.
520 $a This book extends test structure applications described in Microelectronic Test Structures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.
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