國立虎尾科技大學 |

Digital logic design sing Verilog = coding and RTL synthesis /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Digital logic design sing Verilog/ by Vaibbhav Taraate.
其他題名:	coding and RTL synthesis /
作者:	Taraate, Vaibbhav.
出版者:	New Delhi :Springer India : : 2016.,
面頁冊數:	xxiii, 416 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Logic design - Data processing. -
電子資源:	http://dx.doi.org/10.1007/978-81-322-2791-5
ISBN:	9788132227915

Digital logic design sing Verilog = coding and RTL synthesis /
Taraate, Vaibbhav.

Digital logic design sing Verilogcoding and RTL synthesis /[electronic resource] :by Vaibbhav Taraate. - New Delhi :Springer India :2016. - xxiii, 416 p. :ill. (some col.), digital ;24 cm.

Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.

ISBN: 9788132227915

Standard No.: 10.1007/978-81-322-2791-5doiSubjects--Topical Terms:

599477
Logic design
--Data processing.

LC Class. No.: TK7868.L6

Dewey Class. No.: 621.395

Digital logic design sing Verilog = coding and RTL synthesis /
LDR:02431nam a2200313 a 4500 001 864361
003 DE-He213
005 20161021110941.0
006 m d
007 cr nn 008maaau
008 170720s2016 ii s 0 eng d
020 $a 9788132227915 $q (electronic bk.)
020 $a 9788132227892 $q (paper)
024 7 $a 10.1007/978-81-322-2791-5 $2 doi
035 $a 978-81-322-2791-5
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7868.L6
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.395 $2 23
090 $a TK7868.L6 $b T176 2016
100 1 $a Taraate, Vaibbhav. $3 1109142
245 1 0 $a Digital logic design sing Verilog $h [electronic resource] : $b coding and RTL synthesis / $c by Vaibbhav Taraate.
260 $a New Delhi : $c 2016. $b Springer India : $b Imprint: Springer,
300 $a xxiii, 416 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
520 $a This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists.
650 0 $a Logic design $x Data processing. $3 599477
650 0 $a Verilog (Computer hardware description language) $3 563915
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 670219
650 2 4 $a Logic Design. $3 670915
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-81-322-2791-5
950 $a Engineering (Springer-11647)