國立虎尾科技大學 |

Fan-out wafer-level packaging

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Fan-out wafer-level packaging/ by John H. Lau.
作者:	Lau, John H.
出版者:	Singapore :Springer Singapore : : 2018.,
面頁冊數:	xx, 303 p. :ill. (some col.), digital ; : 24 cm.;
Contained By:	Springer eBooks
標題:	Chip scale packaging. -
電子資源:	http://dx.doi.org/10.1007/978-981-10-8884-1
ISBN:	9789811088841

Fan-out wafer-level packaging
Lau, John H.

Fan-out wafer-level packaging[electronic resource] /by John H. Lau. - Singapore :Springer Singapore :2018. - xx, 303 p. :ill. (some col.), digital ;24 cm.

Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration.

This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.

ISBN: 9789811088841

Standard No.: 10.1007/978-981-10-8884-1doiSubjects--Topical Terms:

1062722
Chip scale packaging.

LC Class. No.: TK7870.17 / .L385 2018

Dewey Class. No.: 621.381046

Fan-out wafer-level packaging
LDR:02649nam a2200313 a 4500 001 924954
003 DE-He213
005 20180919155108.0
006 m d
007 cr nn 008maaau
008 190625s2018 si s 0 eng d
020 $a 9789811088841 $q (electronic bk.)
020 $a 9789811088834 $q (paper)
024 7 $a 10.1007/978-981-10-8884-1 $2 doi
035 $a 978-981-10-8884-1
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7870.17 $b .L385 2018
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.381046 $2 23
090 $a TK7870.17 $b .L366 2018
100 1 $a Lau, John H. $3 791741
245 1 0 $a Fan-out wafer-level packaging $h [electronic resource] / $c by John H. Lau.
260 $a Singapore : $c 2018. $b Springer Singapore : $b Imprint: Springer,
300 $a xx, 303 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Patent Issues of Fan-out Wafer-Level Packaging -- Flip Chip Technology vs. FOWLP -- Fan-In Wafer-Level Packaging vs. FOWLP -- Embedded Chip Packaging -- FOWLP: Chip-First and Die Face-Down -- FOWLP: Chip-First and Die Face-Up -- FOWLP: Chip-Last or RDL-First -- FOWLP: PoP with FOWLP -- Fan-Out Panel-Level Packaging (FOPLP) -- 3D Integration -- Heterogeneous Integration.
520 $a This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.
650 0 $a Chip scale packaging. $3 1062722
650 1 4 $a Engineering. $3 561152
650 2 4 $a Circuits and Systems. $3 670901
650 2 4 $a Nanotechnology and Microengineering. $3 722030
650 2 4 $a Optical and Electronic Materials. $3 593919
710 2 $a SpringerLink (Online service) $3 593884
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-981-10-8884-1
950 $a Engineering (Springer-11647)