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Advanced HDL synthesis and SOC proto...

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Taraate, Vaibbhav.

Advanced HDL synthesis and SOC prototyping : = RTL design using Verilog /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Advanced HDL synthesis and SOC prototyping :/ Vaibbhav Taraate.
Reminder of title:	RTL design using Verilog /
Author:	Taraate, Vaibbhav.
Published:	Singapore :Springer, : c2019.,
Description:	xxi, 307 p. :ill. (some col.) ; : 24 cm. ;
Subject:	Microprogramming. -
ISBN:	9789811087752 (cloth) :

Advanced HDL synthesis and SOC prototyping : = RTL design using Verilog /
Taraate, Vaibbhav.

Advanced HDL synthesis and SOC prototyping :RTL design using Verilog /Vaibbhav Taraate. - Singapore :Springer,c2019. - xxi, 307 p. :ill. (some col.) ;24 cm.

Includes bibliographical references and index.

ISBN: 9789811087752 (cloth) :NT5182

LCCN: 2018958948Subjects--Topical Terms:

1022170
Microprogramming.

Dewey Class. No.: 621.3815

Advanced HDL synthesis and SOC prototyping : = RTL design using Verilog /
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010 $a 2018958948
020 $a 9789811087752 (cloth) : $c NT5182
020 $z 9789811087769 (ebook)
035 $a 20676098
040 $a DLC $b eng $c NFU
041 0 # $a eng
082 0 4 $a 621.3815 $2 23
100 1 $a Taraate, Vaibbhav. $3 1109142
245 1 0 $a Advanced HDL synthesis and SOC prototyping : $b RTL design using Verilog / $c Vaibbhav Taraate.
260 # $a Singapore : $b Springer, $c c2019.
300 $a xxi, 307 p. : $b ill. (some col.) ; $c 24 cm.
504 $a Includes bibliographical references and index.
650 # 0 $a Microprogramming. $3 1022170
650 # 0 $a Logic design. $3 561473
650 # 0 $a Electronic circuits. $3 563332

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