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Taraate, Vaibbhav.

Overview
Works: 1 works in 4 publications in 1 languages
Titles
Digital logic design sing Verilog = coding and RTL synthesis / by: SpringerLink (Online service); Taraate, Vaibbhav. (Language materials, printed)
Digital Design Techniques and Exercises = A Practice Book for Digital Logic Design / by: Taraate, Vaibbhav.; SpringerLink (Online service) (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]
ASIC design and synthesis : = RTL design using Verilog / by: Taraate, Vaibbhav. (Language materials, printed)
PLD based design with VHDL = RTL design, synthesis and implementation / by: SpringerLink (Online service); Taraate, Vaibbhav. (Language materials, printed)
Logic Synthesis and SOC Prototyping = RTL Design using VHDL / by: SpringerLink (Online service); Taraate, Vaibbhav. (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]
Digital Logic Design Using Verilog = Coding and RTL Synthesis / by: Taraate, Vaibbhav.; SpringerLink (Online service) (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]
Advanced HDL Synthesis and SOC Prototyping = RTL Design Using Verilog / by: SpringerLink (Online service); Taraate, Vaibbhav. (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]
ASIC Design and Synthesis = RTL Design Using Verilog / by: SpringerLink (Online service); Taraate, Vaibbhav. (Language materials, printed) , [http://id.loc.gov/vocabulary/relators/aut]
SystemVerilog for hardware description : = RTL design and verification / by: Taraate, Vaibbhav. (Language materials, printed)
Advanced HDL synthesis and SOC prototyping : = RTL design using Verilog / by: Taraate, Vaibbhav. (Language materials, printed)
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